MNSC140CORE datasheet(5/80 Pages) FREESCALE

5 / 80 page

MSC8102, Rev. 12

Freescale Semiconductor

60x-Compatible

System Bus

• 64/32-bit data and 32-bit address 60x bus.

• Support for multiple-master designs.

• Four-beat burst transfers (eight-beat in 32-bit wide mode).

• Port size of 64, 32, 16, and 8 controlled by the internal memory controller.

• Bus can access external memory expansion or off-device peripherals, or it can enable an external host

device to access internal resources.

• Slave support, direct access by an external host to internal resources including the M1 and M2 memories.

• On-device arbitration between up to four master devices.

Direct Slave

Interface (DSI)

Provides a 32/64-bit wide slave host interface that operates only as a slave device under the control of an

external host processor.

• 21 bit address, 32/64-bit data.

• Direct access by an external host to on-device resources, including the M1 and the M2 memories.

• Synchronous and asynchronous accesses, with burst capability in the synchronous mode.

• Dual or Single strobe modes.

• Write and Read buffers improves host bandwidth.

• Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.

• Sliding window mode enables access with reduced number of address pins.

• Chip ID decoding enables using one

CS signal for multiple DSPs.

• Broadcast

CS signal enables parallel write to multiple DSPs.

• Big-endian, little-endian, and munged little-endian support.

Memory

Controller

Flexible eight-bank memory controller:

• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-

mode SDRAM machine

• Glueless interface to SRAM, 100 MHz page mode SDRAM, DRAM, EPROM, Flash memory, and other

user-definable peripherals.

• Byte enables for either 64-bit or 32-bit bus width mode.

• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control IPBus

peripherals and internal memories. Each bank has the following features:

• 32-bit address decoding with programmable mask.

• Variable block sizes (32 KB to 4 GB).

• Selectable memory controller machine.

• Two types of data errors check/correction: normal odd/even parity and read-modify-write

(RMW) odd/even parity for single accesses.

• Write-protection capability.

• Control signal generation machine selection on a per-bank basis.

• Support for internal or external masters on the 60x-compatible system bus.

• Data buffer controls activated on a per-bank basis.

• Atomic operation.

• RMW data parity check (on 60x-compatible system bus only).

• Extensive external memory-controller/bus-slave support.

• Parity byte select pin, which enables a fast, glue less connection to RMW-parity devices (on

60x-compatible system bus only).

• Data pipeline to reduce data set-up time for synchronous devices.

Table 3. Buses and Memory Controller (Continued)

Feature

Description

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