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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MNSC140CORE датащи(PDF) 43 Page - Freescale Semiconductor, Inc |
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MNSC140CORE датащи(HTML) 43 Page - Freescale Semiconductor, Inc |
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43 / 80 page  AC Timings MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-13 2.5.5.2 DMA Data Transfers Table 2-14 describes the DMA signal timing. The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-14. Figure 2-8 shows synchronous peripheral interaction. Table 2-14. DMA Signals No. Characteristic Minimum Maximum Units 37 DREQ set-up time before the 50% level of the falling edge of REFCLK 6 — ns 38 DREQ hold time after the 50% level of the falling edge of REFCLK 0.5 — ns 39 DONE set-up time before the 50% level of the rising edge of REFCLK 7 — ns 40 DONE hold time after the 50% level of the rising edge of REFCLK 0.5 — ns 41 DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge 0.5 9 ns Figure 2-8. DMA Signals REFCLK DREQ DONE DACK/DONE/DRACK 37 38 40 39 41 |
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