MNSC140CORE datasheet(73/80 Pages) FREESCALE

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MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

4-1

Design Considerations

This chapter includes design and layout guidelines for manufacturing boards using the MSC8102.

4.1 Power Supply Design and Layout Considerations

The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on

reset. In turn VDDH must not exceed VDD/VCCSYN by more than 2.6 V at any time, including during power-on

reset. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.

Use the following guidelines for power-up and power-down sequences:

• Assert PORESET before applying power and keep the signal driven low until the power reaches the required

minimum power levels. This can be implemented via a weak pull-down resistor.

• CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN

must start toggling before the deassertion of PORESET and after both power supplies have reached nominal

voltage levels.

• To maintain the proper relationship and power-up sequence between the power levels, the recommendation is to

use “bootstrap” diodes between the power rails, as shown in Figure 4-1.

Select the bootstrap diodes such that a nominal VDD/VCCSYN is sourced from the VDDH power supply until the

VDD/VCCSYN power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in

series; each has a forward voltage (VF) of 0.6 V at high currents, so these diodes provide a 2.4 V drop,

maintaining 0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap

diodes will be reverse biased with negligible leakage current. The VF should be effective at the current levels

required by the processor. Do not use diodes with a nominal VF that drops too low at high current. Figure 4-2

shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the

decoupling capacitors should supply the required device current without any drop in voltage on the device pins.

The voltage on the package pins should not drop below 1.5 V even for a very short spikes. This can be achieved

by using the following guidelines:

Figure 4-1.

Bootstrap Diodes for Power-Up Sequencing

I/O Power

Core/PLL

Supply

MUR420

3.3 V (VDDH)

1.6 V (VDD/VCCSYN)

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