MNSC140CORE datasheet(4/80 Pages) FREESCALE

4 / 80 page

MSC8102, Rev. 12

Freescale Semiconductor

Features

The tables in this section list the features of the MSC8102 device.

Table 1. Extended SC140 Cores and Core Memories

Feature

Description

SC140 Core

Four SC140 cores:

• Up to 4400 MMACS using 16 ALUs running at up to 275 MHz.

• A total of 1436 KB of internal SRAM (224 KB per core).

Each SC140 core provides the following:

• Up to 1100 MMACS using an internal 275 MHz clock at 1.6 V. A MAC operation includes a multiply-

accumulate command with the associated data move and pointer update.

• 4 ALUs per SC140 core.

• 16 data registers, 40 bits each.

• 27 address registers, 32 bits each.

• Hardware support for fractional and integer data types.

• Very rich 16-bit wide orthogonal instruction set.

• Up to six instructions executed in a single clock cycle.

• Variable-length execution set (VLES) that can be optimized for code density and performance.

• IEEE 1149.1 JTAG port.

• Enhanced on-device emulation (EOnCE) with real-time debugging capabilities.

Extended Core

Each SC140 core is embedded within an extended core that provides the following:

• 224 KB M1 memory that is accessed by the SC140 core with zero wait states.

• Support for atomic accesses to the M1 memory.

• 16 KB instruction cache, 16 ways.

• A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.

• External cache support by asserting the global signal (GBL) when predefined memory banks are accessed.

• Program Interrupt Controller (PIC).

• Local Interrupt Controller (LIC).

Multi-Core Shared

Memories

• M2 memory (shared memory):

• A 476 KB memory working at the core frequency.

• Accessible from the local bus

• Accessible from all four SC140 cores using the MQBus.

• 4 KB bootstrap ROM.

M2-Accessible

Multi-Core Bus

(MQBus)

• A QBus protocol multi-master bus connecting the four SC140 cores to the M2 memory.

• Data bus access of up to 128-bit read and up to 64-bit write.

• Operation at the SC140 core frequency.

• A central efficient round-robin arbiter controlling SC140 core access on the MQBus.

• Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.

Table 2. Phase-Lock Loop (PLL)

Feature

Description

Internal PLL

• Generates up to 275 MHz core clock and up to 91.67 MHz bus clocks for the 60x-compatible local and

system buses and other modules.

• PLL values are determined at reset based on configuration signal values.

Table 3. Buses and Memory Controller

Feature

Description

Dual-Bus

Architecture

Can be configured to a 32-bit data system bus and a 64-bit data direct slave interface (DSI) or to a 64-bit data

system bus and 32-bit data DSI.

MNSC140CORE датащи(PDF) 4 Page - Freescale Semiconductor, Inc

MNSC140CORE датащи(HTML) 4 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL