MNSC140CORE datasheet(18/80 Pages) FREESCALE

18 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

1-8

Freescale Semiconductor

Signals/Connections

D[0–31]

Input/ Output Data Bus Bits 0–31

In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave drives

the valid data on this bus.

Reserved

DP0

DREQ1

EXT_BR2

Input

Input/Output

Input

The primary configuration selection (default after reset) is reserved.

System Bus Data Parity 0

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 0

pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and

D[0–7].

DMA Request 1

Used by an external peripheral to request DMA service.

External Bus Request 2

An external master asserts this pin to request bus ownership from the internal arbiter.

IRQ1

DP1

DACK1

EXT_BG2

Input

Input/Output

Output

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 1

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 1

pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and

D[8–15].

DMA Acknowledge 1

The DMA drives this output to acknowledge the DMA transaction on the bus.

External Bus Grant 22

The MSC8102 asserts this pin to grant bus ownership to an external bus master.

IRQ2

DP2

DACK2

EXT_DBG2

Input

Input/Output

Output

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 2

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 2

pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and

D[16–23].

DMA Acknowledge 2

The DMA drives this output to acknowledge the DMA transaction on the bus.

External Data Bus Grant 22

The MSC8102 asserts this pin to grant data bus ownership to an external bus master.

IRQ3

DP3

DREQ2

EXT_BR3

Input

Input/Output

Input

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 3

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 3

pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and

D[24–31].

DMA Request 2

Used by an external peripheral to request DMA service.

External Bus Request 32

An external master should assert this pin to request bus ownership from the internal arbiter.

Table 1-5.

DSI, System Bus, and Interrupt Signals (Continued)

Signal Name

Type

Description

MNSC140CORE датащи(PDF) 18 Page - Freescale Semiconductor, Inc

MNSC140CORE датащи(HTML) 18 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL