MNSC140CORE datasheet(38/80 Pages) FREESCALE

38 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

2-8

Freescale Semiconductor

Specifications

Table 2-10 summarizes the reset actions that occur as a result of the different reset sources.

2.5.4.1 Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET and TRST should be asserted external during

power-up. CLKIN may start toggling after VDDH reaches the nominal level, but must start toggling before VDD reaches

0.5 V.

2.5.4.2 Reset Configuration

The MSC8102 has two mechanisms for writing the reset configuration:

• Through the direct slave interface (DSI), or

• Through the system bus

When reset configuration written through the system bus, the MSC8102 uses as a configuration master or as a

configuration slave. If a configuration slave is selected, but no special configuration word is written, a default

configuration word is applied. Fourteen signal levels are sampled on PORESET deassertion to define the Reset

Configuration mode and boot and operating conditions (see Chapter 1 for signal descriptions):

• RSTCONF

• CNFGS

• DSISYNC

• DSI64

• CHIP_ID[0–3]

• BM[0–2]

• SWTE

• MODCK[1–2]

Table 2-10.

Reset Actions for Each Reset Source

Reset Action/Reset Source

Power-On

Reset

(PORESET)

Hard Reset

(HRESET)

Soft Reset (SRESET)

External only

External or

Internal

(Software

Watchdog or

Bus Monitor)

External

JTAG Command:

EXTEST, CLAMP,

or HIGHZ

Configuration pins sampled (refer to Section 2.5.4.1 for

details).

Yes

SPLL and DLL states reset

Yes

System reset configuration write through the DSI

Yes

System reset configuration write though the system bus

Yes

HRESET driven

Yes

SIU registers reset

Yes

IPBus Modules Reset (TDM, UART, timers, DSI, IPBus Master,

GIC, HS, and GPIO)

Yes

SRESET driven

Yes

Depends on command

SC140 extended cores reset

Yes

MQBS reset

Yes

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