MNSC140CORE datasheet(28/80 Pages) FREESCALE

28 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

1-18

Freescale Semiconductor

Signals/Connections

1.7 EOnCE Event and JTAG Test Access Port Signals

The MSC8102 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the

JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the

same two signals EE0 and EE1. The MSC8102 supports the standard set of Test Access Port (TAP) signals defined

by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in

Table 1-8.

GPIO30

TIMER2

TMCLK

Input/Output

Input

General-Purpose Input Output 30

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs.For details, refer to the

MSC8102 Reference Manual GPIO programming model.

Timer 2

Each signal is configured as either input to the counter or output from the counter. For the

configuration of the pin direction, refer to the

MSC8102 Reference Manual.

External TIMER Clock

An external timer can connect directly to the SIU as the SIU Clock.

GPIO31

TIMER3

Input/Output

Input/ Output

General-Purpose Input Output 31

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs. For details, refer to the

MSC8102 Reference Manual GPIO programming model.

Timer 3

Each signal is configured as either input to or output from the counter. For the configuration of the pin

direction, refer to the

MSC8102 Reference Manual.

Table 1-8.

JTAG Test Access Port Signals

Signal Name

Type

Signal Description

EE0

Input

EOnCE Event Bit 0

Used for putting the internal SC140 cores into Debug mode.

EE1

Output

EOnCE Event Bit 1

Indicates that at least one on-chip SC140 core is in Debug mode.

TCK

Input

Test Clock—A test clock signal for synchronizing JTAG test logic.

TDI

Input

Test Data Input—A test data serial signal for test instructions and data. TDI is sampled on the rising

edge of TCK and has an internal pull-up resistor.

TDO

Output

Test Data Output—A test data serial signal for test instructions and data. TDO can be tri-stated. The

signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge

of TCK.

TMS

Input

Test Mode Select—Sequences the test controller’s state machine, is sampled on the rising edge of

TCK, and has an internal pull-up resistor.

TRST

Input

Test Reset—Asynchronously initializes the test controller, has an internal pull-up resistor, and must

be asserted after power up.

Table 1-7.

GPIO, TDM, UART, and Timer Signals (Continued)

Signal Name

Type

Description

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