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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MNSC140CORE датащи(PDF) 39 Page - Freescale Semiconductor, Inc |
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MNSC140CORE датащи(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 80 page  AC Timings MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-9 2.5.4.3 Reset Timing Tables Table 2-11 and Figure 2-5 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or through the system bus. Table 2-11. Timing for a Reset Configuration Write through the DSI or System Bus No. Characteristics Expression Min Max Unit 1 Required external PORESET duration minimum • CLKIN = 33 MHz • CLKIN = 75 MHz 16/CLKIN 484.8 213.3 — ns 2 Delay from deassertion of external PORESET to deassertion of internal PORESET • CLKIN = 33 MHz • CLKIN = 75 MHz 1024/CLKIN 31.03 13.65 µs µs 3 Delay from de-assertion of internal PORESET to SPLL lock • CLKIN = 33 MHz • CLKIN = 75 MHz 800/(CLKIN/PDF) (pre-division factor) 48.5 32.0 µs µs 4 Delay from SPLL lock to DLL lock. • DLL enabled REFCLK = 33 Mhz REFCLK = 75 Mhz • DLL disabled 3073/REFCLK — 93.12 40.97 0.0 µs µs µs 5 • Delay from SPLL and DLL lock to HRESET de-assertion • DLL enabled REFCLK = 33 Mhz REFCLK = 75 Mhz • DLL disabled REFCLK = 33 Mhz REFCLK = 75 Mhz 3585/REFCLK 512/REFCLK 108.64 47.5 15.52 6.83 µs µs µs µs 6 Delay from SPLL and DLL lock to SRESET de-assertion • DLL enabled REFCLK = 33 Mhz REFCLK = 75 Mhz • DLL disabled REFCLK = 33 Mhz REFCLK = 75 Mhz 3588/REFCLK 515/REFCLK 108.73 47.84 15.61 6.87 µs µs µs µs Note: Timings are not tested, but are guaranteed by design. Figure 2-5. Timing Diagram for a Reset Configuration Write PORESET Internal HRESET Input Output (I/O) SRESET Output (I/O) RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1-2] Host programs Word SPLL and DLL are locked (no external indication) PORESET Reset Configuration pins are sampled 1 2 MODCK[3–5], are ready for SPLL. DLLDIS bits 1 + 2 3 + 4 5 6 When DLL is disabled, reset period is shortened by 3073 bus clocks. SPLL and DLL locking period. Reset configuration write sequence occurs during this period. |
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