MNSC140CORE datasheet(74/80 Pages) FREESCALE

74 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

4-2

Freescale Semiconductor

Design Considerations

— For the core supply, use a voltage regulator rated at 1.6 V with nominal rating of at least 3 A. This rating does

not reflect actual average current draw, but is recommended because it resists changes imposed by transient

spikes and has better voltage recovery time than lower current rated supplies.

— Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 4-2 shows

three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If

possible, mount at least one of the capacitors directly below the MSC8102 device.

Each VCC and VDD pin on the MSC8102 should be provided with a low-impedance path to the board power supply.

Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive

distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at least four 0.1 µF

by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and

associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per

capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes.

All output pins on the MSC8102 have fast rise and fall times. PCB trace interconnection length should be

minimized in order to minimize undershoot and reflections caused by these fast output switching times. This

recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six inches are

recommended. For the DSI control signals in Synchronous mode, make sure that the layout supports the DSI AC

timing requirements and minimizes any signal crosstalk. Capacitance calculations should consider all device loads

as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes

especially critical in systems with higher capacitive loads because these loads create higher transient currents in the

VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply

pins: VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to

the one in Figure 4-3. To filter as much noise as possible, place the circuit as close as possible to VCCSYN. The 0.01-

µF capacitor should be closest to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-

Ω

resistor to VDD. These traces should be kept short and direct. Provide an extremely low impedance path to ground

Figure 4-2.

Core Power Supply Decoupling

Power supply

Voltage Regulator

High Freq. capacitors

(very low ESR and ESL)

Bulk/Tantalum capacitors

with low ESR and ESL

MSC8102

maximum IR drop

of 15 mV at 1 A

Note: Use at least three capacitors.

Lmax = 2 cm

One 0.01 µF capacitor

for every 3 Core supply

(Imin = 3 A)

pads.

1.6 V

Each capacitor must be at least 150

µF.

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