MNSC140CORE datasheet(37/80 Pages) FREESCALE

37 / 80 page

AC Timings

MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

2-7

2.5.4

Reset Timing

The MSC8102 has several inputs to the reset logic:

• Power-on reset (PORESET)

• External hard reset (HRESET)

• External soft reset (SRESET)

• Software watchdog reset

• Bus monitor reset

• Host reset command through JTAG

All MSC8102 reset sources are fed into the reset controller, which takes different actions depending on the source

of the reset. The reset status register indicates the most recent sources to cause a reset. Table 2-9 describes the reset

sources.

Table 2-9.

Reset Sources

Name

Direction

Description

Power-on reset

(PORESET)

Input

Initiates the power-on reset flow that resets the MSC8102 and configures various attributes of the MSC8102.

On PORESET, the entire MSC8102 device is reset. SPLL and DLL states are reset, HRESET and SRESET

are driven, the SC140 extended cores are reset, and system configuration is sampled. The clock mode

(MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64 bits port or a System

Bus 64 bits port are configured only when PORESET is asserted.

External Hard

reset

(HRESET)

Input/

Output

Initiates the hard reset flow that configures various attributes of the MSC8102. While HRESET is asserted,

SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and SRESET are driven,

the SC140 extended cores are reset, and system configuration is sampled. The most configurable features are

reconfigure. These features are defined in the 32-bit hard reset configuration word described in

Hard Reset

Configuration Word section of the Reset chapter in the MSC8102 Reference Manual.

External Soft

reset

(SRESET)

Input/

Output

Initiates the soft reset flow. The MSC8102 detects an external assertion of SRESET only if it occurs while the

MSC8102 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the SC140

extended cores are reset, and system configuration is maintained.

Software

watchdog reset

Internal

When the MSC8102 watchdog count reaches zero, a software watchdog reset is signalled. The enabled

software watchdog event then generates an internal hard reset sequence.

Bus monitor

reset

Internal

When the MSC8102 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled bus

monitor event then generates an internal hard reset sequence.

Host reset

command

through the

TAP

Internal

When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the soft reset

signal and an internal soft reset sequence is generated.

MNSC140CORE датащи(PDF) 37 Page - Freescale Semiconductor, Inc

MNSC140CORE датащи(HTML) 37 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL