MNSC140CORE datasheet(40/80 Pages) FREESCALE

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MSC8102 Quad Core Digital Signal Processor, Rev. 12

2-10

Freescale Semiconductor

Specifications

2.5.5

System Bus Access Timing

2.5.5.1 Core Data Transfers

Generally, all MSC8102 bus and system output signals are driven from the rising edge of the reference clock

(REFCLK). The REFCLK is either the DLLIN signal or, if DLL is disabled, the CLKOUT signal. Memory controller

signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1,

T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), as Figure 2-6 shows.

Figure 2-6 is a graphical representation of the internal ticks.

The UPM machine and GPCM machine outputs change on the internal tick determined by the memory controller

configuration. The AC specifications are relative to the internal tick. SDRAM machine outputs change only on the

REFCLK

rising edge.

Figure 2-6.

Internal Tick Spacing for Memory Controller Signals

Table 2-12.

AC Timing for SIU Inputs

No.

Characteristic

Value2

Units

Hold time for all signals after the 50% level of the REFCLK rising edge

11a

ARTRY/ABB/TS set-up time before the 50% level of the REFCLK rising edge

4.5

11b

DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising edge

4.3

11c

AACK set-up time before the 50% level of the REFCLK rising edge

5.0

11d

TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge

•

Pipeline mode

•

Non-pipeline mode

3.7

5.0

Data bus set-up time before REFCLK rising edge in Normal mode

•

Pipeline mode

•

Non-pipeline mode

2.3

4.9

Data bus set-up time before the 50% level of the REFCLK rising edge in ECC and PARITY modes

•

Pipeline mode

•

Non-pipeline mode

2.6

DP set-up time before the 50% level of the REFCLK rising edge

•

Pipeline mode

•

Non-pipeline mode

2.3

6.5

15a

Address bus set-up time before the 50% level of the REFCLK rising edge

•

Extra cycle mode (SIUBCR[EXDD] = 0)

•

No extra cycle mode (SIUBCR[EXDD] = 1)

3.1

6.9

15b

Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the REFCLK rising edge

•

Extra cycle mode (SIUBCR[EXDD] = 0)

•

No extra cycle mode (SIUBCR[EXDD] = 1)

5.5

7.6

161

PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge

4.0

Notes:

Synchronous operation. Asynchronous operation may have a higher set-up time.

Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.

REFCLK

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