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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MNSC140CORE датащи(PDF) 47 Page - Freescale Semiconductor, Inc |
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MNSC140CORE датащи(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 80 page  AC Timings MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-17 2.5.6.2 DSI Synchronous Mode Table 2-16. DSI Inputs—Synchronous Mode Number Characteristic Expression Minimum Maximum Units 120 HCLKIN Cycle Time1 HTC 14.3 55.6 ns 121 HCLKIN high pulse width (0.5 ± 0.1) × HTC 5.7 33.3 ns 122 HCLKIN Low pulse width (0.5 ± 0.1) × HTC 5.7 33.3 ns 123 HA[11–29] inputs set-up time — 2.4 — ns 124 HD[0–63] inputs set-up time — 3.4 — ns 125 HCID[0–4] inputs set-up time — 3.3 — ns 126 All other inputs set-up time — 2.5 — ns 127 All inputs hold time — 2.2 — ns Notes: 1. Values are based on a frequency range of 18–70 MHz. See Table 2-6 for HCLKIN limits. Table 2-17. DSI Outputs—Synchronous Mode Number Characteristic Minimum Maximum Units 128 HCLKIN high to HD[0–63] output active 2.0 — 129 HCLKIN high to HD[0–63] output valid — 8.6 130 HD[0–63] output hold time 1.8 — 131 HCLKIN high to HD[0–63] output high impedance — 9.4 132 HCLKIN high to HTA output active 1.5 — 133 HCLKIN high to HTA output valid — 9.0 134 HTA output hold time 1.7 — 135 HCLKIN high to HTA high impedance — 5.2 Figure 2-12. DSI Synchronous Mode Signals Timing Diagram HCLKIN HA[11–29] input signals All other input signals HD[0–63] output signals HTA output signal HD[0–63] input signals 120 127 123 126 127 122 121 131 130 129 128 133 135 134 132 HCID[0–4] input signals 125 127 127 124 |
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