MNSC140CORE datasheet(26/80 Pages) FREESCALE

26 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

1-16

Freescale Semiconductor

Signals/Connections

GPIO19

TDM1RCLK

DACK2

Input/Output

Output

General-Purpose Input Output 19

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs. For details, refer to the

MSC8102 Reference Manual GPIO programming model.

TDM1 Receive Clock

The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For

configuration details, refer to the

MSC8102 Reference Manual chapter describing TDM operation.

DMA Acknowledge 2

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

GPIO20

TDM1RDAT

Input/Output

Input/ Output

General-Purpose Input Output 20

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs. For details, refer to the

MSC8102 Reference Manual GPIO programming model.

TDM1 Serial Receiver Data

The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM 1. For

configuration details, refer to the

MSC8102 Reference Manual chapter describing TDM operation.

GPIO21

TDM0TSYN

Input/Output

General-Purpose Input Output 21

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs. For details, refer to the

MSC8102 Reference Manual GPIO programming model.

TDM0 Transmit frame Sync

Transmit Frame Sync for TDM 0.

GPIO22

TDM0TCLK

DONE2

DRACK2

Input/Output

Input

Input/Output

Output

General-Purpose Input Output 22

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs.For details, refer to the

MSC8102 Reference Manual GPIO programming model.

TDM 0 Transmit Clock

Transmit Clock for TDM 0.

DMA Done 2

Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling

this peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal

channel closing.

Note:

See the

MSC8102 Reference Manual chapters on DMA and GPIO for information on

configuring the DRACK or DONE mode and pin direction.

DMA Data Request Acknowledge 2

Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral

request.

GPIO23

TDM0TDAT

IRQ13

Input/Output

Input

General-Purpose Input Output 23

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated

outputs. For details, refer to the

MSC8102 Reference Manual GPIO programming model.

TDM0 Serial Transmitter Data

The transmit data signal for TDM 0. As an output, this can be the DATA_D data signal for TDM 0. For

configuration details, refer to the

MSC8102 Reference Manual chapter describing TDM operation.

Interrupt Request 13

One of fifteen external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Table 1-7.

GPIO, TDM, UART, and Timer Signals (Continued)

Signal Name

Type

Description

MNSC140CORE датащи(PDF) 26 Page - Freescale Semiconductor, Inc

MNSC140CORE датащи(HTML) 26 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL