MNSC140CORE datasheet(75/80 Pages) FREESCALE

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Connectivity Guidelines

MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

4-3

for GNDSYN. Bypass GNDSYN to VCCSYN with a 0.01-µF capacitor as close as possible to the chip package. For best

results, place this capacitor on the backside of the PCB aligned with the depopulated void on the MSC8102 located

in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13.

Note:

See the MSC8102 Design Checklist (AN2506) for additional information.

4.2 Connectivity Guidelines

Unused output pins can be disconnected, and unused input pins should be connected to their non-active value,

except for the following:

• If the DSI is unused (bit DDR[DSIDIS] is set), then HCS and HBCS must be tied to VDD and all the rest of the DSI

signals can be disconnected.

• When the DSI uses Synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled

either up or down depending on design requirements.

• HDST can be disconnected if the DSI is in Big-endian mode, or if the DSI is in Little-endian mode and

DCR[DSRFA] bit is set.

• When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3]

and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7] must be tied to VDD.

• When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3]

must be tied to VDD.

• When the DSI is in Asynchronous mode, HBRST and HCLKIN should either be disconnected or tied to VDD.

• When using the DSI in Synchronous mode, use special care when laying out the control signals. Test the layout

to make sure that it supports the specified DSI AC timing values and minimizes signal cross-coupling.

• The following signals can be disconnected in single-master mode (BCR[EBM] is reset): BG, DBG, EXT_BG[2–3],

EXT_DBG[2-3]

, GBL and TS.

• The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.

• In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In

other modes, they must be pulled up.

Figure 4-3.

VCCSYN Bypass

VDD

0.01 µF

10 µF

VCCSYN

Ω

10nH

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