MNSC140CORE datasheet(17/80 Pages) FREESCALE

17 / 80 page

Direct Slave Interface, System Bus, and Interrupt Signals

MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

1-7

IRQ5

BADDR29

Input

Output

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Bus Burst Address 291

There are five burst address output pins, which are outputs of the memory controller. These pins connect

directly to burstable memory devices without internal address incrementors controlled by the MSC8102

memory controller.

BADDR28

Output

Burst Address 28

There are five burst address output pins, which are outputs of the memory controller. These pins connect

directly to burstable memory devices without internal address incrementors controlled by the MSC8102

memory controller.

BADDR27

Output

Burst Address 27

There are five burst address output pins, which are outputs of the memory controller. These pins connect

directly to burstable memory devices without internal address incrementors controlled by the MSC8102

memory controller.

Input/Output

Bus Request2

When an external arbiter is used, the MSC8102 asserts this pin as an output to request ownership of the

bus. When the MSC8102 controller is used as an internal arbiter, an external master asserts this pin as an

input to request bus ownership.

Input/ Output Bus Grant

When the MSC8102 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to an

external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus ownership

to the MSC8102.

DBG

Input/ Output Data Bus Grant2

When the MSC8102 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership

to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data bus

ownership to the MSC8102.

ABB

IRQ4

Input/Output

Input

Address Bus Busy1

The MSC8102 asserts this pin as an output for the duration of the address bus tenure. Following an AACK,

which terminates the address bus tenure, the MSC8102 deasserts ABB for a fraction of a bus cycle and

then stops driving this pin. The MSC8102 does not assume bus ownership as long as it senses this pin is

asserted as an input by an external bus master.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DBB

IRQ5

Input/Output

Input

Data Bus Busy1

The MSC8102 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which

terminates the data bus tenure, the MSC8102 deasserts DBB for a fraction of a bus cycle and then stops

driving this pin. The MSC8102 does not assume data bus ownership as long as it senses that this pin is

asserted as an input by an external bus master.

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Input/Output

Bus Transfer Start

Assertion of this pin signals the beginning of a new address bus tenure. The MSC8102 asserts this signal

when one of its internal bus masters begins an address tenure. When the MSC8102 senses that this pin is

asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled,

access internal MSC8102 resources, memory controller support).

AACK

Input/ Output Address Acknowledge

A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal

terminates the address tenure.

ARTRY

Input/ Output Address Retry

Assertion of this signal indicates that the bus master should retry the bus transaction. An external master

asserts this signal to enforce data coherency with its caches and to prevent deadlock situations.

Table 1-5.

DSI, System Bus, and Interrupt Signals (Continued)

Signal Name

Type

Description

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