MNSC140CORE datasheet(19/80 Pages) FREESCALE

19 / 80 page

Direct Slave Interface, System Bus, and Interrupt Signals

MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

1-9

IRQ4

DP4

DACK3

EXT_DBG3

Input

Input/Output

Output

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 4

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 4

pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and

D[32–39].

DMA Acknowledge 3

The DMA drives this output to acknowledge the DMA transaction on the bus.

External Data Bus Grant 3

The MSC8102 asserts this pin to grant data bus ownership to an external bus master.

IRQ5

DP5

DACK4

EXT_BG3

Input

Input/Output

Output

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 5

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 5

pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and

D[40–47].

DMA Acknowledge 4

The DMA drives this output to acknowledge the DMA transaction on the bus.

External Bus Grant 3

The MSC8102 asserts this pin to grant bus ownership to an external bus.

IRQ6

DP6

DREQ3

Input

Input/Output

Input

Interrupt Request 6

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 6

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 6

pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and

D[48–55].

DMA Request 3

Used by an external peripheral to request DMA service.

IRQ7

DP7

DREQ4

Input

Input/Output

Input

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 7

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 7

pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and

D[56–63].

DMA Request 4

Used by an external peripheral to request DMA service.

Input/Output

Transfer Acknowledge

Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion indicates the

termination of the transfer. For burst transfers, TA is asserted eight times to indicate the transfer of eight

data beats, with the last assertion indicating the termination of the burst transfer.

TEA

Input/Output

Transfer Error Acknowledge

Assertion indicates a failure of the data tenure transaction.The masters within the MSC8102 monitor the

state of this pin. The MSC8102 internal bus monitor can assert this pin if it identifies a bus transfer that does

not complete.

Table 1-5.

DSI, System Bus, and Interrupt Signals (Continued)

Signal Name

Type

Description

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