MNSC140CORE datasheet(53/80 Pages) FREESCALE

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MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

3-1

Packaging

This chapter provides information on the MSC8102 package, including diagrams of the package pinouts and tables

showing how the signals discussed in Chapter 1 are allocated. The MSC8102 is available in a 431-pin High

Temperature Coefficient for Expansion Flip Chip-Ceramic Ball Grid Array (FC-CBGA (HCTE)).

3.1 FC-CBGA (HCTE) Package Description

Figure 3-1 and Figure 3-2 show top and bottom views of the FC-CBGA (HCTE) package, including pinouts. To

conform to JDEC requirements, the package is based on a 23

× 23 position (20 × 20 mm) layout with the outside

perimeter depopulated. Therefore, ball position numbering starts with B2. Signal names shown in the figures are

typically the signal assigned after reset. Signals that are only used during power-on reset (SWTE, DSISYNC, DSI64,

MODCK[1–2]

, CNFGS, and CHIP_ID[0–3]) are not shown in these figures if there is another signal assigned to the pin

after reset. Also, there are several signals that are designated as IRQ lines immediately after reset, but represent

duplicate IRQ lines that should be reconfigured by the user. To represent these signals uniquely in the figures, the

second functions (BADDR[29–31], DP[1–7], and INT_OUT) are used.

Table 3-1 lists the MSC8102 signals alphabetically by signal name. Connections with multiple names are listed

individually by each name. Signals with programmable polarity are shown both as signals which are asserted low

(default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is

listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity

are shown in this table only with their default name (asserted low).

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