PIC18F23K22-ESLASHML datasheet(138/496 Pages) MICROCHIP

138 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 138

Preliminary

 2010 Microchip Technology Inc.

10.2

PORTB Registers

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB. Setting

a TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., disable the output driver). Clearing a

TRISB bit (= 0) will make the corresponding PORTB

pin an output (i.e., enable the output driver and put the

contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

EXAMPLE 10-2:

INITIALIZING PORTB

10.2.1

PORTB OUTPUT PRIORITY

Each PORTB pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are briefly described here. For additional

information, refer to the appropriate section in this data

sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the higher priority.

Table 10-4 lists the PORTB pin functions from the

highest to the lowest priority.

Analog input functions, such as ADC, comparator and

SR Latch inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output functions may control the pin when it is in Analog

mode with the priority shown below.

10.3

Additional PORTB Pin Functions

PORTB pins RB<7:4> have an interrupt-on-change

option. All PORTB pins have a weak pull-up option.

10.3.1

WEAK PULL-UPS

Each of the PORTB pins has an individually controlled

weak internal pull-up. When set, each bit of the WPUB

cleared, the RBPU bit of the INTCON2 register enables

pull-ups on all pins which also have their corresponding

WPUB bit set. When set, the RBPU bit disables all

weak pull-ups. The weak pull-up is automatically turned

off when the port pin is configured as an output. The

pull-ups are disabled on a Power-on Reset.

10.3.2

INTERRUPT-ON-CHANGE

Four of the PORTB pins (RB<7:4>) are individually

configurable as interrupt-on-change pins. Control bits

in the IOCB register enable (when set) or disable (when

clear) the interrupt function for each pin.

When set, the RBIE bit of the INTCON register enables

interrupts on all pins which also have their

corresponding IOCB bit set. When clear, the RBIE bit

disables all interrupt-on-changes.

Only pins configured as inputs can cause this interrupt

to occur (i.e., any RB<7:4> pin configured as an output

is excluded from the interrupt-on-change comparison).

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTB. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTB Change Interrupt flag

bit (RBIF) in the INTCON register.

This interrupt can wake the device from the Sleep

mode, or any of the Idle modes. The user, in the

Interrupt Service Routine, can clear the interrupt in the

following manner:

a) Any read or write of PORTB to clear the mis-

match condition (except when PORTB is the

source or destination of a MOVFF instruction).

b) Execute at least one instruction after reading or

writing PORTB, then clear the flag bit, RBIF.

MOVLB

0xF

; Set BSR for banked SFRs

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

CLRF

LATB

; Alternate method

; to clear output

; data latches

MOVLW

0F0h

; Value for init

MOVWF

ANSELB ; Enable RB<3:0> for

; digital input pins

; (not required if config bit

; PBADEN is clear)

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Note:

On a Power-on Reset, RB<5:0> are

configured as analog inputs by default and

read as ‘0’; RB<7:6> are configured as

digital inputs.

When the PBADEN Configuration bit is set

to ‘1’, RB<5:0> will alternatively be

configured as digital inputs on POR.

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