PIC18F23K22-ESLASHML datasheet(47/496 Pages) MICROCHIP

47 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 47

PIC18(L)F2X/4XK22

3.0

POWER-MANAGED MODES

PIC18(L)F2X/4XK22 devices offer a total of seven

operating modes for more efficient power manage-

ment. These modes provide a variety of options for

selective power conservation in applications where

resources may be limited (i.e., battery-powered

devices).

There are three categories of power-managed modes:

• Run modes

• Idle modes

• Sleep mode

These categories define which portions of the device

are clocked and sometimes, what speed. The Run and

Idle modes may use any of the three available clock

sources (primary, secondary or internal oscillator

block). The Sleep mode does not use a clock source.

The power-managed modes include several power-

saving features offered on previous PIC® microcontroller

devices. One of the clock switching features allows the

controller to use the secondary oscillator (SOSC) in

place of the primary oscillator. Also included is the Sleep

mode, offered by all PIC® microcontroller devices, where

all device clocks are stopped.

3.1

Selecting Power-Managed Modes

Selecting a power-managed mode requires two

decisions:

• Whether or not the CPU is to be clocked

• The selection of a clock source

The IDLEN bit (OSCCON<7>) controls CPU clocking,

while the SCS<1:0> bits (OSCCON<1:0>) select the

clock source. The individual modes, bit settings, clock

sources and affected modules are summarized in

Table 3-1.

3.1.1

CLOCK SOURCES

The SCS<1:0> bits allow the selection of one of three

clock sources for power-managed modes. They are:

• the primary clock, as defined by the FOSC<3:0>

Configuration bits

• the secondary clock (the SOSC oscillator)

• the internal oscillator block

3.1.2

ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS<1:0> bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. Refer to

Section 2.9 “Clock Switching” for more information.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator select

bits, or changing the IDLEN bit, prior to issuing a SLEEP

instruction. If the IDLEN bit is already configured

correctly, it may only be necessary to perform a SLEEP

instruction to switch to the desired mode.

TABLE 3-1:

POWER-MANAGED MODES

Mode

OSCCON Bits

Module Clocking

Available Clock and Oscillator Source

IDLEN(1)

SCS<1:0>

CPU

Peripherals

Sleep

N/A

Off

None – All clocks are disabled

PRI_RUN

N/A

Clocked

Primary – LP, XT, HS, RC, EC and Internal

Oscillator Block(2).

This is the normal full-power execution mode.

SEC_RUN

N/A

Clocked

Secondary – SOSC Oscillator

RC_RUN

N/A

Clocked

Internal Oscillator Block(2)

PRI_IDLE

100

Off

Clocked

Primary – LP, XT, HS, HSPLL, RC, EC

SEC_IDLE

101

Off

Clocked

Secondary – SOSC Oscillator

RC_IDLE

11x

Off

Clocked

Internal Oscillator Block(2)

Note 1:

IDLEN reflects its value when the SLEEP instruction is executed.

Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.

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