PIC18F23K22-ESLASHML datasheet(22/496 Pages) MICROCHIP

22 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 22

Preliminary

 2010 Microchip Technology Inc.

724

RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4

RA5

I/O

TTL

Digital I/O.

C2OUT

CMOS Comparator C2 output.

SRNQ

TTL

SR Latch Q output.

SS1

TTL

SPI slave select input (MSSP1).

HLVDIN

Analog High/Low-Voltage Detect input.

AN4

Analog Analog input 4.

RA6/CLKO/OSC2

RA6

I/O

TTL

Digital I/O.

CLKO

—

In RC mode, OSC2 pin outputs CLKOUT which

has 1/4 the frequency of OSC1 and denotes the

instruction cycle rate.

OSC2

—

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

RA7/CLKI/OSC1

RA7

I/O

TTL

Digital I/O.

CLKI

CMOS External clock source input. Always associated

with pin function OSC1.

OSC1

Oscillator crystal input or external clock source

input ST buffer when configured in RC mode;

CMOS otherwise.

RB0/INT0/FLT0/SRI/AN12

RB0

I/O

TTL

Digital I/O.

INT0

External interrupt 0.

FLT0

PWM Fault input for ECCP Auto-Shutdown.

SRI

SR Latch input.

AN12

Analog Analog input 12.

RB1/INT1/C12IN3-/AN10

RB1

I/O

TTL

Digital I/O.

INT1

External interrupt 1.

C12IN3-

Analog Comparators C1 and C2 inverting input.

AN10

Analog Analog input 10.

RB2/INT2/CTED1/AN8

RB2

I/O

TTL

Digital I/O.

INT2

External interrupt 2.

CTED1

CTMU Edge 1 input.

AN8

Analog Analog input 8.

RB3/CTED2/P2A/CCP2/C12IN2-/AN9

RB3

I/O

TTL

Digital I/O.

CTED2

CTMU Edge 2 input.

P2A(2)

CMOS Enhanced CCP2 PWM output.

CCP2(2)

I/O

Capture 2 input/Compare 2 output/PWM 2 output.

C12IN2-

Analog Comparators C1 and C2 inverting input.

AN9

Analog Analog input 9.

TABLE 1-3:

PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Name

Type

Buffer

Type

Description

PDIP

TQFP

QFN

UQFN

Legend:

TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power.

Note

1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX

and CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,

CCP3MX and CCP2MX are clear.

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