PIC18F23K22-ESLASHML datasheet(98/496 Pages) MICROCHIP

98 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 98

Preliminary

 2010 Microchip Technology Inc.

6.2.2

TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch register is used to

hold 8-bit data during data transfers between program

memory and data RAM.

6.2.3

TBLPTR – TABLE POINTER

The Table Pointer (TBLPTR) register addresses a byte

within the program memory. The TBLPTR is comprised

of three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

program memory space. The 22nd bit allows access to

the device ID, the user ID and the Configuration bits.

The Table Pointer register, TBLPTR, is used by the

TBLRD and TBLWT instructions. These instructions can

update the TBLPTR in one of four ways based on the

table operation. These operations on the TBLPTR

affect only the low-order 21 bits.

6.2.4

TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR

determine which byte is read from program memory

directly into the TABLAT register.

When a TBLWT is executed the byte in the TABLAT

holding registers constitute a write block which varies

depending on the device (see Table 6-1).The 3, 4, or 5

LSbs of the TBLPTRL register determine which specific

address within the holding register block is written to.

The MSBs of the Table Pointer have no effect during

TBLWT operations.

When a program memory write is executed the entire

holding register block is written to the Flash memory at

the address determined by the MSbs of the TBLPTR.

The 3, 4, or 5 LSBs are ignored during Flash memory

writes. For more detail, see Section 6.5 “Writing to

Flash Program Memory”.

When an erase of program memory is executed, the

16 MSbs of the Table Pointer register (TBLPTR<21:6>)

point to the 64-byte block that will be erased. The Least

Significant bits (TBLPTR<5:0>) are ignored.

Figure 6-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 6-1:

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 6-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

Example

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*-

TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+*

TBLPTR is incremented before the read/write

TABLE ERASE/WRITE

TABLE WRITE

TABLE READ – TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

TBLPTR<n:0>(1)

TBLPTR<21:n+1>(1)

Note 1: n = 6 for block sizes of 64 bytes.

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