PIC18F23K22-ESLASHML datasheet(51/496 Pages) MICROCHIP

51 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 51

PIC18(L)F2X/4XK22

3.3

Sleep Mode

The Power-Managed Sleep mode in the PIC18(L)F2X/

4XK22 devices is identical to the legacy Sleep mode

offered in all other PIC® microcontroller devices. It is

entered by clearing the IDLEN bit of the OSCCON

down the selected oscillator (Figure 3-4) and all clock

source status bits are cleared.

Entering the Sleep mode from either Run or Idle mode

does not require a clock switch. This is because no

clocks are needed once the controller has entered

Sleep. If the WDT is selected, the LFINTOSC source

will continue to operate. If the SOSC oscillator is

enabled, it will also continue to run.

When a wake event occurs in Sleep mode (by interrupt,

Reset or WDT time-out), the device will not be clocked

until the clock source selected by the SCS<1:0> bits

becomes ready (see Figure 3-5), or it will be clocked

from the internal oscillator block if either the Two-Speed

Start-up or the Fail-Safe Clock Monitor are enabled

(see Section 24.0 “Special Features of the CPU”). In

either case, the OSTS bit is set when the primary clock

is providing the device clocks. The IDLEN and SCS bits

are not affected by the wake-up.

3.4

Idle Modes

The Idle modes allow the controller’s CPU to be

selectively shut down while the peripherals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is

executed, the peripherals will be clocked from the clock

source selected by the SCS<1:0> bits; however, the CPU

will not be clocked. The clock source status bits are not

affected. Setting IDLEN and executing a SLEEP instruc-

tion provides a quick method of switching from a given

Run mode to its corresponding Idle mode.

If the WDT is selected, the LFINTOSC source will con-

tinue to operate. If the SOSC oscillator is enabled, it will

also continue to run.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

time-out, or a Reset. When a wake event occurs, CPU

execution is delayed by an interval of TCSD while it

becomes ready to execute code. When the CPU

begins executing code, it resumes with the same clock

source for the current Idle mode. For example, when

waking from RC_IDLE mode, the internal oscillator

block will clock the CPU and peripherals (in other

words, RC_RUN mode). The IDLEN and SCS bits are

not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS<1:0> bits.

FIGURE 3-4:

TRANSITION TIMING FOR ENTRY TO SLEEP MODE

OSC1

Peripheral

Sleep

Program

Counter

Clock

CPU

Clock

PC + 2

PIC18F23K22-E/ML датащи(PDF) 51 Page - Microchip Technology

PIC18F23K22-E/ML датащи(HTML) 51 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL