PIC18F23K22-ESLASHML datasheet(53/496 Pages) MICROCHIP

53 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 53

PIC18(L)F2X/4XK22

FIGURE 3-7:

TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

3.4.3

RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the periph-

erals continue to be clocked from the internal oscillator

block from the HFINTOSC multiplexer output. This

mode allows for controllable power conservation during

Idle periods.

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If the

device is in another Run mode, first set IDLEN, then set

the SCS1 bit and execute SLEEP. It is recommended

that SCS0 also be cleared, although its value is

ignored, to maintain software compatibility with future

devices. The HFINTOSC multiplexer may be used to

select a higher clock frequency by modifying the IRCF

bits before executing the SLEEP instruction. When the

clock source is switched to the HFINTOSC multiplexer,

the primary oscillator is shut down and the OSTS bit is

cleared.

If the IRCF bits are set to any non-zero value, or either

the INTSRC or MFIOSEL bits are set, the HFINTOSC

output is enabled. Either the HFIOFS or the MFIOFS

bits become set, after the HFINTOSC output stabilizes

after an interval of TIOBST. For information on the

HFIOFS and MFIOFS bits, see Table 3-2.

Clocks to the peripherals continue while the

HFINTOSC source stabilizes. The HFIOFS and

MFIOFS bits will remain set if the IRCF bits were

previously set at a non-zero value or if INTSRC was set

before the SLEEP instruction was executed and the

HFINTOSC source was already stable. If the IRCF bits

and INTSRC are all clear, the HFINTOSC output will

not be enabled, the HFIOFS and MFIOFS bits will

remain clear and there will be no indication of the

current clock source.

When a wake event occurs, the peripherals continue to

be clocked from the HFINTOSC multiplexer output.

After a delay of TCSD following the wake event, the CPU

begins executing code being clocked by the

HFINTOSC multiplexer. The IDLEN and SCS bits are

not affected by the wake-up. The LFINTOSC source

will continue to run if either the WDT or the Fail-Safe

Clock Monitor is enabled.

OSC1

Peripheral

Program

CPU Clock

Clock

Counter

Wake Event

TCSD

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