PIC18F23K22-ESLASHML datasheet(52/496 Pages) MICROCHIP

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PIC18(L)F2X/4XK22

DS41412C-page 52

Preliminary

 2010 Microchip Technology Inc.

FIGURE 3-5:

TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

3.4.1

PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm-up” or transition from another

oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then clear the SCS bits and execute SLEEP.

Although the CPU is disabled, the peripherals continue

to be clocked from the primary clock source specified

by the FOSC<3:0> Configuration bits. The OSTS bit

remains set (see Figure 3-6).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become ready to execute instructions. After the wake-

up, the OSTS bit remains set. The IDLEN and SCS bits

are not affected by the wake-up (see Figure 3-7).

3.4.2

SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the SOSC

oscillator. This mode is entered from SEC_RUN by set-

ting the IDLEN bit and executing a SLEEP instruction. If

the device is in another Run mode, set the IDLEN bit

first, then set the SCS<1:0> bits to ‘01’ and execute

SLEEP. When the clock source is switched to the SOSC

oscillator, the primary oscillator is shut down, the OSTS

bit is cleared and the SOSCRUN bit is set.

When a wake event occurs, the peripherals continue to

be clocked from the SOSC oscillator. After an interval

of TCSD following the wake event, the CPU begins exe-

cuting code being clocked by the SOSC oscillator. The

IDLEN and SCS bits are not affected by the wake-up;

the SOSC oscillator continues to run (see Figure 3-7).

FIGURE 3-6:

TRANSITION TIMING FOR ENTRY TO IDLE MODE

Q3 Q4 Q1 Q2

OSC1

Peripheral

Program

PLL Clock

Q3 Q4

Output

CPU Clock

Q2 Q3 Q4 Q1 Q2

Clock

Counter

PC + 6

PC + 4

Q1 Q2 Q3 Q4

Wake Event

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST(1)

TPLL(1)

OSTS bit set

PC + 2

Note:

The SOSC oscillator should already be

running prior to entering SEC_IDLE mode.

At least one of the secondary oscillator

enable bits (SOSCGO, T1SOSCEN,

T3SOSCEN or T5SOSCEN) must be set

when the SLEEP instruction is executed.

Otherwise, the main system clock will con-

tinue to operate in the previously selected

mode and the corresponding IDLE mode

will be entered (i.e., PRI_IDLE or

RC_IDLE).

Peripheral

Program

PC + 2

OSC1

CPU Clock

Clock

Counter

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