PIC18F23K22-ESLASHML datasheet(72/496 Pages) MICROCHIP

72 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 72

Preliminary

 2010 Microchip Technology Inc.

5.1.2.3

PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the

ability to push values onto the stack and pull values off

the stack without disturbing normal program execution

is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

TOSU, TOSH and TOSL can be modified to place data

or a return address on the stack.

The PUSH instruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

The POP instruction discards the current TOS by decre-

menting the Stack Pointer. The previous value pushed

onto the stack then becomes the TOS value.

5.1.2.4

Stack Full and Underflow Resets

Device Resets on Stack Overflow and Stack Underflow

conditions are enabled by setting the STVREN bit in

Configuration Register 4L. When STVREN is set, a full

or underflow will set the appropriate STKFUL or

STKUNF bit and then cause a device Reset. When

STVREN is cleared, a full or underflow condition will set

the appropriate STKFUL or STKUNF bit but not cause

a device Reset. The STKFUL or STKUNF bits are

cleared by the user software or a Power-on Reset.

5.1.3

FAST REGISTER STACK

A fast register stack is provided for the Status, WREG

and BSR registers, to provide a “fast return” option for

interrupts. The stack for each register is only one level

deep and is neither readable nor writable. It is loaded

with the current value of the corresponding register

when the processor vectors for an interrupt. All inter-

rupt sources will push values into the stack registers.

The values in the registers are then loaded back into

their associated registers if the RETFIE, FAST

instruction is used to return from the interrupt.

If both low and high priority interrupts are enabled, the

stack registers cannot be used reliably to return from

low priority interrupts. If a high priority interrupt occurs

while servicing a low priority interrupt, the stack register

values stored by the low priority interrupt will be

overwritten. In these cases, users must save the key

registers by software during a low priority interrupt.

If interrupt priority is not used, all interrupts may use the

fast register stack for returns from interrupt. If no

interrupts are used, the fast register stack can be used

to restore the Status, WREG and BSR registers at the

end of a subroutine call. To use the fast register stack

for a subroutine call, a CALL label, FAST instruction

must be executed to save the Status, WREG and BSR

registers to the fast register stack. A RETURN, FAST

instruction is then executed to restore these registers

from the fast register stack.

Example 5-1 shows a source code example that uses

the fast register stack during a subroutine call and

return.

STKPTR: STACK POINTER REGISTER

R/C-0

U-0

R/W-0

STKFUL(1)

STKUNF(1)

—

STKPTR<4:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented

C = Clearable only bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed

0 = Stack has not become full or overflowed

bit 6

STKUNF: Stack Underflow Flag bit(1)

1 = Stack Underflow occurred

0 = Stack Underflow did not occur

bit 5

Unimplemented: Read as ‘0’

bit 4-0

STKPTR<4:0>: Stack Pointer Location bits

Note 1:

Bit 7 and bit 6 are cleared by user software or by a POR.

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