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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC18F23K22-E/ML датащи(PDF) 64 Page - Microchip Technology |
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PIC18F23K22-E/ML датащи(HTML) 64 Page - Microchip Technology |
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64 / 496 page  PIC18(L)F2X/4XK22 DS41412C-page 64 Preliminary 2010 Microchip Technology Inc. FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration Power-up(2) and Brown-out Exit from Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) —— RC, RCIO 66 ms(1) —— INTIO1, INTIO2 66 ms(1) —— Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET |
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