PIC18F23K22-ESLASHML datasheet(54/496 Pages) MICROCHIP

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PIC18(L)F2X/4XK22

DS41412C-page 54

Preliminary

 2010 Microchip Technology Inc.

3.5

Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is

triggered by any one of the following:

• an interrupt

•a Reset

• a Watchdog Time-out

This section discusses the triggers that cause exits

from power-managed modes. The clocking subsystem

actions are discussed in each of the power-managed

modes (see Section 3.2 “Run Modes”, Section 3.3

“Sleep Mode” and Section 3.4 “Idle Modes”).

3.5.1

EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit from an Idle mode or the Sleep mode to

a Run mode. To enable this functionality, an interrupt

source must be enabled by setting its enable bit in one

of the INTCON or PIE registers. The exit sequence is

initiated when the corresponding interrupt flag bit is set.

The instruction immediately following the SLEEP

instruction is executed on all exits by interrupt from Idle

or Sleep modes. Code execution then branches to the

interrupt vector if the GIE/GIEH bit of the INTCON

without branching (see Section 9.0 “Interrupts”).

A fixed delay of interval TCSD following the wake event

is required when leaving Sleep and Idle modes. This

delay is required for the CPU to prepare for execution.

Instruction execution resumes on the first clock cycle

following this delay.

3.5.2

EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending

on which power-managed mode the device is in when

the time-out occurs.

If the device is not executing code (all Idle modes and

Sleep mode), the time-out will result in an exit from the

power-managed

mode

(see

Section 3.2

“Run

Modes” and Section 3.3 “Sleep Mode”). If the device

is executing code (all Run modes), the time-out will

result in a WDT Reset (see Section 24.2 “Watchdog

Timer (WDT)”).

The WDT timer and postscaler are cleared by any one

of the following:

• executing a SLEEP instruction

• executing a CLRWDT instruction

• the loss of the currently selected clock source

when the Fail-Safe Clock Monitor is enabled

• modifying the IRCF bits in the OSCCON register

when the internal oscillator block is the device

clock source

3.5.3

EXIT BY RESET

Exiting Sleep and Idle modes by Reset causes code

execution to restart at address 0. See Section 4.0

“Reset” for more details.

The exit delay time from Reset to the start of code

execution depends on both the clock sources before

and after the wake-up and the type of oscillator. Exit

delays are summarized in Table 3-3.

3.5.4

EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Certain exits from power-managed modes do not

invoke the OST at all. There are two cases:

• PRI_IDLE mode, where the primary clock source

is not stopped and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these instances, the primary clock source either

does not require an oscillator start-up delay since it is

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (RC, EC, INTOSC,

and INTOSCIO modes). However, a fixed delay of

interval TCSD following the wake event is still required

when leaving Sleep and Idle modes to allow the CPU

to prepare for execution. Instruction execution resumes

on the first clock cycle following this delay.

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