PIC18F23K22-ESLASHML datasheet(139/496 Pages) MICROCHIP

139 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 139

PIC18(L)F2X/4XK22

A mismatch condition will continue to set the RBIF flag bit.

Reading or writing PORTB will end the mismatch

condition and allow the RBIF bit to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After either one of these Resets, the

RBIF flag will continue to be set if a mismatch is present.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

10.3.3

ALTERNATE FUNCTIONS

PORTB is multiplexed with several peripheral functions

(Table 10-5). The pins have TTL input buffers. Some of

these pin functions can be relocated to alternate pins

using the Control fuse bits in CONFIG3H. RB5 is the

default pin for P2B (28-pin devices). Clearing the

P2BMX bit moves the pin function to RC0. RB5 is also

the default pin for the CCP3/P3A peripheral pin. Clear-

ing the CCP3MX bit moves the pin function to the RC6

pin (28-pin devices) or RE0 (40/44-pin devices).

Two other pin functions, T3CKI and CCP2/P2A, can be

relocated from their default pins to PORTB pins by

clearing the control fuses in CONFIG3H. Clearing

T3CMX and CCP2MX moves the pin functions to RB5

and RB3, respectively.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF

interrupt flag may not get set. Furthermore,

since a read or write on a port affects all bits

of that port, care must be taken when using

multiple pins in Interrupt-on-change mode.

Changes on one pin may not be seen while

servicing changes on another pin.

TABLE 10-5:

PORTB I/O SUMMARY

Function

TRIS

Setting

ANSEL

Setting

Type

Buffer

Type

Description

RB0/INT0/CCP4/

FLT0/SRI/SS2/

AN12

RB0

DIG

LATB<0> data output; not affected by analog input.

TTL

PORTB<0> data input; disabled when analog input

enabled.

INT0

External interrupt 0.

CCP4(3)

DIG

Compare 4 output/PWM 4 output.

Capture 4 input.

FLT0

PWM Fault input for ECCP auto-shutdown.

SRI

SR Latch input.

SS2(3)

TTL

SPI slave select input (MSSP2).

AN12

Analog input 12.

RB1/INT1/P1C/

SCK2/SCL2/

C12IN3-/AN10

RB1

DIG

LATB<1> data output; not affected by analog input.

PORTB<1> data input; disabled when analog input

enabled.

INT1

External Interrupt 1.

P1C(3)

DIG

Enhanced CCP1 PWM output 3.

SCK2(3)

DIG

MSSP2 SPI Clock output.

MSSP2 SPI Clock input.

SCL2(3)

ODIG

MSSP2 I2CTM Clock output.

II2C

MSSP2 I2CTM Clock input.

C12IN3-

Comparators C1 and C2 inverting input.

AN10

Analog input 10.

Legend:

AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM

= Schmitt Trigger input with I2C.

Note 1:

Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

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