PIC18F23K22-ESLASHML datasheet(133/496 Pages) MICROCHIP

133 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 133

PIC18(L)F2X/4XK22

10.0 I/O PORTS

Depending on the device selected and features

enabled, there are up to five ports available. All pins of

the I/O ports are multiplexed with one or more alternate

functions from the peripheral features on the device. In

general, when a peripheral is enabled, that pin may not

be used as a general purpose I/O pin.

Each port has five registers for its operation. These

registers are:

• TRIS register (data direction register)

• PORT register (reads the levels on the pins of the

device)

• LAT register (output latch)

• ANSEL register (analog input control)

• SLRCON register (port slew rate control)

The Data Latch (LAT register) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 10-1.

FIGURE 10-1:

GENERIC I/O PORT

OPERATION

10.1

PORTA Registers

PORTA is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA. Setting

a TRISA bit (= 1) will make the corresponding PORTA

pin an input (i.e., disable the output driver). Clearing a

TRISA bit (= 0) will make the corresponding PORTA pin

an output (i.e., enable the output driver and put the

contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it, will write to the PORT latch.

The Data Latch (LATA) register is also memory mapped.

Read-modify-write operations on the LATA register read

and write the latched output value for PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input and one of the comparator outputs to

become the RA4/T0CKI/C1OUT pin. Pins RA6 and

RA7 are multiplexed with the main oscillator pins; they

are enabled as oscillator or I/O pins by the selection of

the main oscillator in the Configuration register (see

Section 24.1 “Configuration Bits” for details). When

they are not used as port pins, RA6 and RA7 and their

associated TRIS and LAT bits are read as ‘0’.

The other PORTA pins are multiplexed with analog

inputs, the analog VREF+ and VREF- inputs, and the

comparator voltage reference output. The operation of

pins RA<3:0> and RA5 as analog is selected by setting

the ANSELA<5, 3:0> bits in the ANSELA register which

is the default setting after a Power-on Reset.

Pins RA0 through RA5 may also be used as comparator

inputs or outputs by setting the appropriate bits in the

CM1CON0 and CM2CON0 registers.

The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input.

All other PORTA pins have TTL input levels and full

CMOS output drivers.

The TRISA register controls the drivers of the PORTA

pins, even when they are being used as analog inputs.

The user should ensure the bits in the TRISA register

are maintained set when using them as analog inputs.

EXAMPLE 10-1:

INITIALIZING PORTA

Data

Bus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Input

Buffer

I/O pin(1)

RD LAT

or Port

Note 1:

I/O pins have diode protection to VDD and VSS.

TRISx

ANSELx

Note:

On a Power-on Reset, RA5 and RA<3:0>

are configured as analog inputs and read

as ‘0’. RA4 is configured as a digital input.

MOVLB

0xF

; Set BSR for banked SFRs

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

CLRF

LATA

; Alternate method

; to clear output

; data latches

MOVLW

E0h

; Configure I/O

MOVWF

ANSELA ; for digital inputs

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISA

; Set RA<3:0> as inputs

; RA<5:4> as outputs

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