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PIC18F23K22-E/ML датащи(PDF) 129 Page - Microchip Technology |
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PIC18F23K22-E/ML датащи(HTML) 129 Page - Microchip Technology |
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129 / 496 page ![]() 2010 Microchip Technology Inc. Preliminary DS41412C-page 129 PIC18(L)F2X/4XK22 REGISTER 9-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IP: Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TMR5GIP: TMR5 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority |
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