ATtiny167-ESSZ datasheet(101/282 Pages) ATMEL

101 / 282 page

101

7728D–AVR–07/09

ATtiny87/ATtiny167

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM01:0 bit setting. Table 10-1 shows the COM0A1:0 bit functionality when the WGM01:0

bits are set to a normal or CTC mode (non-PWM).

Table 10-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page

94 for more details.

Table 10-3 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase cor-

rect PWM mode.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode”

on page 95 for more details.

• Bit 5:2 – Res: Reserved Bits

These bits are reserved in the ATtiny87/167 and will always read as zero.

Table 10-1.

Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

Toggle OC0A on Compare Match.

Clear OC0A on Compare Match.

Set OC0A on Compare Match.

Table 10-2.

Compare Output Mode, Fast PWM Mode

(1)

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

Clear OC0A on Compare Match.

Set OC0A at BOTTOM (non-inverting mode).

Set OC0A on Compare Match.

Clear OC0A at BOTTOM (inverting mode).

Table 10-3.

Compare Output Mode, Phase Correct PWM Mode

(1)

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

Clear OC0A on Compare Match when up-counting.

Set OC0A on Compare Match when down-counting.

Set OC0A on Compare Match when up-counting.

Clear OC0A on Compare Match when down-counting.

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