XIO2001IPNP datasheet(127/145 Pages) TI2

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switching noise. The 3.3-V pins are named VDD_33 and supply power to most of the input and output cells. Both

the VDD_15 and VDD_33 supplies must have 0.1-μF bypass capacitors to VSS (ground) in order for proper

operation. The recommendation is one capacitor for each power pin. When placing and connecting all bypass

capacitors, high-speed board design rules must be followed.

9.4.2 1.5-V and 3.3-V Analog Supplies

Both 1.5-V and 3.3-V analog power is required by the XIO2001. Since circuit noise on the analog power

terminals must be minimized, a Pi filter is recommended. All VDDA_15 pins must be connected together and

share one Pi filter. All VDDA_33 terminals must be connected together and share a second Pi filter.

Both the 1.5-V and 3.3-V analog supplies must have 0.1-μF bypass capacitors connected to VSSA (ground) in

order for proper operation. The recommendation is one capacitor for each power terminal. In addition, one 1000-

pF capacitor per Pi filter is recommended. This 1000-pF capacitor is attached to the device side of the Pi filter

and to VSSA (ground). High-speed board design rules must be followed when connecting bypass capacitors to

VDDA and VSSA.

9.4.3 1.5-V PLL Supply

The XIO2001 requires a 1.5-V power supply for the internal PLL (VDDPLL_15). Circuit noise on PLL power must

be minimized. A Pi-filter with a 200-mA inductor and 220 Ω @ 100 MHz is recommended for this terminal. The

PLL power must have a 0.1- μ F bypass capacitor connected to VSS. In addition, a 1000- pF capacitor per Pi-

filter is recommended, this 1000-pF capacitor is attached to the device side of the Pi- filter and to VSSA (analog-

ground).

9.4.4 Power-Up/Down Sequencing

Note

The power sequencing recommendations in this section exclude the VDD_33_AUX terminal.

All XIO2001 analog and digital power pins must be controlled during the power-up and power-down sequence.

Absolute maximum power pin ratings must not be exceeded to prevent damaging the device. All power pins

must remain within 3.6 V to prevent damaging the XIO2001.

9.4.5 Power Supply Filtering Recommendations

To meet the PCI-Express jitter specifications, low-noise power supplies are required on several of the XIO2001

voltage terminals. The power terminals that require low-noise power include VDDA_15 and VDDA_33. This section

provides guidelines for the filter design to create low-noise power sources.

The least expensive solution for low-noise power sources is to filter existing 3.3-V and 1.5-V power supplies.

This solution requires analysis of the noise frequencies present on the power supplies. The XIO2001 has

external interfaces operating at clock rates of 25 MHz, 33 MHz, 50 MHz, 66 MHz, 100 MHz, 125 MHz, and 2.5

GHz. Other devices located near the XIO2001 may produce switching noise at different frequencies. Also, the

power supplies that generate the 3.3 V and 1.5 V power rails may add low frequency ripple noise. Linear

regulators have feedback loops that typically operate in the 100 kHz range. Switching power supplies typically

have operating frequencies in the 500 KHz range. When analyzing power supply noise frequencies, the first,

third, and fifth harmonic of every clock source should be considered.

Critical analog circuits within the XIO2001 must be shielded from this power supply noise. The fundamental

requirement for a filter design is to reduce power supply noise to a peak-to-peak amplitude of less than 25 mV.

This maximum noise amplitude should apply to all frequencies from 0 Hz to 12.5 GHz.

The following information should be considered when designing a power supply filter:

• Ideally, the series resonance frequency for each filter component should be greater than the fifth harmonic of

the maximum clock frequency. With a maximum clock frequency of 1.25 GHz, the third harmonic is 3.75 GHz

and the fifth harmonic is 6.25 GHz. Finding inductors and capacitors with a series resonance frequency

above 6.25 GHz is both difficult and expensive. Components with a series resonance frequency in the 4 to 6

GHz range are a good compromise.

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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