XIO2001IPNP datasheet(124/145 Pages) TI2

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9.2.5.2 Detailed Design Procedure

See previous Section 9.2.1.2.

9.3 Layout

9.3.1 Layout Guidelines

In motherboard designs there is an additional clock delay on the PCI add-in cards. In order to make the overall

lengths of the PCI Clock Signals be the same, a rule has been made, which states that the length of the Clock

Signal will be fixed to 2.5" on PCI add-in cards. The motherboard design requires that the length of the Clock

Signal going to the PCI add-in slots will be less by 2.5" in comparison with the other Clock Signals that do not go

to a PCI add-in slot. With the PCI add-in cards inserted, the Clock Signals lengths match. In a design where

there is no add-in slot, the length of the PCI Clock Signals should match. A typical embedded system has all PCI

devices on the board itself. In such case, the lengths of clock nets should match.

There is no matching requirement on the length of the Address/Data signals with respect to Clock Signal,

though, there is a limitation on the maximum length of the Address/Data signal length depending upon the PCI

Bus speed. The length matching of clock signals in PCI bus is not very critical. It is however, often, not too

difficult to match it within 100 mils. The PCI Clock Signals should be slightly longer than the longest trace on the

PCI bus. When 100 mil recommendations become impractical due to board space constraints, this can be

relaxed up to a recommended maximum of 250 mils.

All 32 bit PCI slots must be placed so the slot can be put on the board as either a 3 V or a 5 V slot. All pins used

as keying pins (A12, A13, A50, A51, B12,B13, B50, B51) should be put on the board and connected to the GND

plane. Mounting holes must be placed on either side of the socket.

(CTXn + TXn) and (CTXp + TXp) are a 100 W differential impedance pair (50 W single ended) and must be

length matched to within 5 mils. i.e. CTXp must be within 5 mils of CTXn, TXp must be within 5 mils of TXn, and

(CTXp + TXp) must be within 5 mils of (CTXn + TXn). The coupling capacitors must be placed as close to the

PCI Express Edge connector as possible.

RXp and RXn are a 100 W differential impedance pair (50 W single ended) and must be length matched to

within 5 mils.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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