TMP86CS64AFG datasheet(176/202 Pages) TOSHIBA

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Page 166

16. Synchronous Serial Interface (SIO2)

16.6 Transfer Mode

TMP86CS64AFG

When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is

necessary to read the received data and write the data to be transmitted next before starting the next shift oper-

ation. When an external clock is used, the transfer speed is determined by the maximum delay between genera-

tion of an interrupt request and the received data are read and the data to be transmitted next are written.

The transmit/receive operation is ended by clearing SIO2CR1<SIOS> to “0” or setting SIO2CR1<SIOINH> to

“1” in INTSIO2 interrupt service program.

When SIO2CR1<SIOS> is cleared, the current data are transferred to the buffer. After SIO2CR1<SIOS>

cleared, the transmitting/receiving is ended at the time that the final bit of the data has been transmitted.

That the transmitting/receiving has ended can be determined from the status of SIO2SR<SIOF>.

SIO2SR<SIOF> is cleared to “0” when the transmitting/receiving is ended.

When SIO2CR1<SIOINH> is set, the transmit/receive operation is immediately ended and SIO2SR<SIOF>

is cleared to “0”.

If it is necessary to change the number of words in external clock operation, SIO2CR1<SIOS> should be

cleared to “0”, then SIO2CR2<BUF> must be rewritten after confirming that SIO2SR<SIOF> has been cleared

to “0”.

If it is necessary to change the number of words in internal clock, during automatic-wait operation which

occurs after completion of transmit/receive operation, SIO2CR2<BUF> must be rewritten before reading and

writing of the receive/transmit data.

Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the

transfer mode, end receiving by clearing SIO2CR1<SIOS> to “0”, read the last data and then switch the trans-

fer mode.

Figure 16-11 Transfer / Receive Mode (Example: 8bit, 1word transfer, Internal clock)

Clear SIOS

DBR

Read out (c)

Write (a)

Read out (d)

Write (b)

SCK2 pin

(output)

SO2 pin

INTSIO2 interrupt

SIO2CR1<SIOS>

SIO2SR<SIOF>

SIO2SR<SEF>

SI2 pin

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