TMP86CS64AFG datasheet(175/202 Pages) TOSHIBA

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Page 165

TMP86CS64AFG

When an external clock is used, the shift operation is synchronized with the external clock; therefore, the

previous data are read before the next data are transferred to the data buffer register. If the previous data have

not been read, the next data will not be transferred to the data buffer register and the receiving of any more data

will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay

between the time when the interrupt request is generated and when the data received have been read.

The receiving is ended by clearing SIO2CR1<SIOS> to “0” or setting SIO2CR1<SIOINH> to “1” in buffer

full interrupt service program.

When SIO2CR1<SIOS> is cleared, the current data are transferred to the buffer. After SIO2CR1<SIOS>

cleared, the receiving is ended at the time that the final bit of the data has been received. That the receiving has

ended can be determined from the status of SIO2SR<SIOF>. SIO2SR<SIOF> is cleared to “0” when the

receiving is ended. After confirmed the receiving termination, the final receiving data is read. When

SIO2CR1<SIOINH> is set, the receiving is immediately ended and SIO2SR<SIOF> is cleared to “0”. (The

received data is ignored, and it is not required to be read out.)

If it is necessary to change the number of words in external clock operation, SIO2CR1<SIOS> should be

cleared to “0” then SIO2CR2<BUF> must be rewritten after confirming that SIO2SR<SIOF> has been cleared

to “0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation

which occurs after completion of data receiving, SIO2CR2<BUF> must be rewritten before the received data is

read out.

Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the

transfer mode, end receiving by clearing SIO2CR1<SIOS> to “0”, read the last data and then switch the trans-

fer mode.

Figure 16-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock)

16.6.3 8-bit transfer / receive mode

After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first

to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIO2CR1<SIOS> to “1”.

When transmitting, the data are output from the SO2 pin at leading edges of the serial clock. When receiving,

the data are input to the SI2 pin at the trailing edges of the serial clock. When the all receive is enabled, 8-bit

data are transferred from the shift register to the data buffer register. An INTSIO2 interrupt is generated when

the number of data words specified with the SIO2CR2<BUF> has been transferred. Usually, read the receive

data from the buffer register in the interrupt service. The data buffer register is used for both transmitting and

receiving; therefore, always write the data to be transmitted after reading the all received data.

When the internal clock is used, a wait is initiated until the received data are read and the next transfer data

are written. A wait will not be initiated if even one transfer data word has been written.

DBR

Clear SIOS

Read out

SCK2 pin

(Output)

SI2 pin

INTSIO2 Interrupt

SIO2CR1<SIOS>

SIO2SR<SIOF>

SIO2SR<SEF>

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