TMP86CS64AFG datasheet(153/202 Pages) TOSHIBA

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Page 143

TMP86CS64AFG

Figure 14-8 Generation of Overrun Error

Note:Receive operations are disabled until the overrun error flag UARTSR<OERR> is cleared.

14.10.4Receive Data Buffer Full

Loading the received data in RDBUF sets receive data buffer full flag UARTSR<RBFL> to "1". The

UARTSR<RBFL> is cleared to “0” when the RDBUF is read after reading the UARTSR.

Figure 14-9 Generation of Receive Data Buffer Full

Note:If the overrun error flag UARTSR<OERR> is set during the period between reading the UARTSR and reading

the RDBUF, it cannot be cleared by only reading the RDBUF. Therefore, after reading the RDBUF, read the

UARTSR again to check whether or not the overrun error flag which should have been cleared still remains

set.

14.10.5Transmit Data Buffer Empty

When no data is in the transmit buffer TDBUF, UARTSR<TBEP> is set to “1”, that is, when data in TDBUF

are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag

UARTSR<TBEP> is set to “1”. The UARTSR<TBEP> is cleared to “0” when the TDBUF is written after

reading the UARTSR.

Final bit

Stop

Shift register

xxxx0*

1xxxx0

yyyy

xxx0**

RXD1 pin

UARTSR<OERR>

INTTRX interrupt

After reading UARTSR then

RDBUF clears OERR.

RDBUF

UARTSR<RBFL>

Final bit

Stop

Shift register

xxxx0*

1xxxx0

xxxx

yyyy

xxx0**

RXD1 pin

UARTSR<RBFL>

INTTRX interrupt

RDBUF

After reading UARTSR then

RDBUF clears RBFL.

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