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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86CS64AFG датащи(PDF) 142 Page - Toshiba Semiconductor |
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TMP86CS64AFG датащи(HTML) 142 Page - Toshiba Semiconductor |
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142 / 202 page  Page 132 13. 8-Bit TimerCounter 6 (TC6) 13.1 Configuration TMP86CS64AFG 13.3.3 Programmable Divider Output (PDO) Mode The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by count- ing with the internal clock. When a match between the up-counter and the TC6DR value is detected, the logic level output from the PDO6 pin is switched to the opposite state and INTTC6 interrupt request is generated. The up-counter is cleared at this time and then counting is continued. When a match between the up-counter and the TC6DR value is detected, the logic level output from the PDO6 pin is switched to the opposite state again and INTTC6 interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued. When the timer is stopped, the PDO6 pin is high. Therefore, if the timer is stopped when the PDO6 pin is low, the duty pulse may be shorter than the programmed value. Figure 13-2 PDO Mode Timing Chart Example :Generating 1024 Hz pulse (fc = 16.0 Mhz) LD (TC6CR), 00000110B : Sets the PDO mode. (TC6M = 10, TC6CK = 001) LD (TC6DR), 3DH : 1/1024 ÷ 27/fc ÷ 2 (half cycle period) = 3DH LD (TC6CR), 00100110B : Start TC6 Internal clock Counter Match detect 0 12 n 0 12 n 0 1 2 n 01 2 n 0 1 n TC6DR PDO6 pin INTTC6 interrupt request Timer F/F |
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