TMP86CS64AFG datasheet(119/202 Pages) TOSHIBA

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TMP86CS64AFG

10.3.2 Event Counter Mode

In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC3 pin.

When a match between the up-counter and TC3DRA value is detected, an INTTC3 interrupt is generated and

up-counter is cleared. After being cleared, the up-counter restarts counting at each rising edge of the input

pulse to the TC3 pin. Since a match is detected at the falling edge of the input pulse to TC3 pin, an INTTC3

interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in

TC3DRA.

The maximum applied frequencies are shown in Table 10-2. The pulse width larger than one machine cycle

is required for high-going and low-going pulses.

Setting TC3CR<ACAP> to 1 captures the up-counter value into TC3DRB with the auto-capture function.

The count value during a timer operation can be checked by the read instruction to TC3DRB.

Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB.

(Figure 10-2)

Figure 10-4 Event Counter Mode Timing Chart

Example :Inputting 50 Hz pulse to TC3, and generating interrupts every 0.5 s

(TC3CR), 00001110B

: Sets the clock mode

(TC3DRA), 19H

: 0.5 s

÷ 1/50 = 25 = 19H

(TC3CR), 00011110B

: Starts TC3.

Table 10-2 Maximum Frequencies Applied to TC3

Minimum Pulse Width

NORMAL1/2, IDLE1/2 mode

SLOW1/2, SLEEP1/2 mode

High-going

22/fc

22/fs

Low-going

22/fc

22/fs

INTTC3 interrupt

TC3 pin input

Counter

TC3DRA

Match detect

Counter clear

Timer start

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