TMP86CS64AFG datasheet(116/202 Pages) TOSHIBA

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Page 106

10. 8-Bit TimerCounter 3 (TC3)

10.1 Configuration

TMP86CS64AFG

10.2 TimerCounter Control

The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers

(TC3DRA and TC3DRB).

Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care

Note 2: Set the operating mode and source clock when TimerCounter stops (TC3S = 0).

Note 3: To set the timer registers, the following relationship must be satisfied.

TC3DRA > 1 (Timer/event counter mode)

Note 4: Auto-capture (ACAP) can be used only in the timer and event counter modes.

Note 5: When the read instruction is executed to TC3CR, the bit 5 and 7 are read as a don’t care.

Note 6: Do not program TC3DRA when the timer is running (TC3S = 1).

Note 7: When the STOP mode is entered, the start control (TC3S) is cleared to 0 automatically, and the timer stops. After

the STOP mode is exited, TC3S must be set again to use the timer counter.

Timer Register and Control Register

TC3DRA

(0010H)

543

Read/Write (Initial value: 1111 1111)

TC3DRB

(0011H)

Read only (Initial value: 1111 1111)

TC3CR

(0012H)

543

ACAP

TC3S

TC3CK

TC3M

(Initial value: *0*0 0000)

ACAP

Auto capture control

0: –

1: Auto capture

R/W

TC3S

TC3 start control

0: Stop and counter clear

1: Start

R/W

TC3CK

TC3 source clock select

[Hz]

NORMAL1/2, IDLE1/2 mode

Divider

SLOW1/2,

SLEEP1/2

mode

R/W

DV7CK

= 0DV7CK = 1

DV1CK=0

DV1CK=1

DV1CK=0

DV1CK=1

000

fc/213

fc/214

fs/25

DV11

fs/25

001

fc/212

fc/213

fs/24

DV10

fs/24

010

fc/211

fc/212

fs/23

DV9

fs/23

011

fc/210

fc/211

fs/22

DV8

fs/22

100

fc/29

fc/210

fs/2

DV7

fs/2

101

fc/28

fc/29

fc/28

fc/29

DV6

–

110

fc/27

fc/28

fc/27

fc/28

DV5

–

111

External clock (TC3 pin input)

TC3M

TC3 operating mode

select

0: Timer/event counter mode

1: Capture mode

R/W

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