ST72324BJ2 datasheet(99/188 Pages) STMICROELECTRONICS

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ST72324B

On-chip peripherals

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10.4.6

Low power modes

Using the SPI to wake up the MCU from Halt mode

In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a

SPIF interrupt. The data received is subsequently read from the SPIDR register when the

software is running (interrupt vector fetch). If multiple data transfers have been performed

before software clears the SPIF bit, then the OVR bit is set by hardware.

Note:

When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to

perform an extra communications cycle to bring the SPI from Halt mode state to normal

state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution:

The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS

pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. Therefore,

if Slave selection is configured as external (see Slave Select management on page 93),

make sure the master drives a low level on the SS pin when the slave enters Halt mode.

10.4.7

Interrupts

10.4.8

SPI registers

SPI Control Register (SPICR)

Table 52.

Effect of low power modes on SPI

Mode

Description

Wait

No effect on SPI.

SPI interrupt events cause the device to exit from Wait mode.

Halt

SPI registers are frozen.

In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an

interrupt with Exit from Halt mode capability. The data received is subsequently read from

the SPIDR register when the software is running (interrupt vector fetching). If several data

are received before the wake-up event, then an overrun error is generated. This error can

be detected after the fetch of the interrupt routine that woke up the device.

Table 53.

SPI interrupt control/wake-up capability(1)

The SPI interrupt events are connected to the same interrupt vector (see Section 7: Interrupts). They

generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC

Interrupt event

Event flag

Enable control bit

Exit from WAIT Exit from HALT

SPI end of transfer event

SPIF

SPIE

Yes

Master mode fault event

MODF

Overrun error

OVR

SPICR

Reset value: 0000 xxxx (0xh)

654

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR[1:0]

R/W

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