ST72324BJ2 datasheet(77/188 Pages) STMICROELECTRONICS

77 / 188 page

ST72324B

On-chip peripherals

77/188

If the timer clock is an external clock, the formula is:

Where:

∆t

= Output compare period (in seconds)

fEXT

= External timer clock frequency (in hertz)

Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:

Reading the SR register while the OCFi bit is set.

An access (read or write) to the OCiLR register.

The following procedure is recommended to prevent the OCFi bit from being set between

the time it is read and the write to the OCiR register:

●

Write to the OCiHR register (further compares are inhibited).

●

Read the SR register (first step of the clearance of the OCFi bit, which may be already

set).

●

Write to the OCiLR register (enables the output compare function and clears the OCFi

bit).

Note:

After a processor write cycle to the OCiHR register, the output compare function is inhibited

until the OCiLR register is also written.

If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt could be generated if the OCIE bit is set.

In both internal and external clock modes, OCFi and OCMPi are set while the counter value

equals the OCiR register value (see Figure 44 on page 78 for an example with fCPU/2 and

Figure 45 on page 78 for an example with fCPU/4). This behavior is the same in OPM or

PWM mode.

The output compare functions can be used both for generating external events on the

OCMPi pins even if the input capture mode is also used.

The value in the 16-bit OCiR register and the OLVi bit should be changed after each

successful comparison in order to control an output waveform or establish a new elapsed

timeout.

Forced output compare capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit

has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The

OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both one pulse mode and PWM mode.

∆ OCiR = ∆t * fEXT

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