ST72324BJ2 datasheet(101/188 Pages) STMICROELECTRONICS

101 / 188 page

ST72324B

On-chip peripherals

101/188

SPI Control/Status Register (SPICSR)

fCPU/16

fCPU/32

fCPU/64

fCPU/128

SPICSR

Reset value: 0000 0000 (00h)

654

SPIF

WCOL

OVR

MODF

Reserved

SOD

SSM

SSI

R/W

Table 56.

SPICSR register description

Bit

Name

Function

SPIF

Serial Peripheral data transfer flag

This bit is set by hardware when a transfer has been completed. An interrupt is

generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an

access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been cleared

1: Data transfer between the device and an external device has been completed.

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the

SPICSR register is read.

6WCOL

Write Collision status

This bit is set by hardware when a write to the SPIDR register is done during a

transmit sequence. It is cleared by a software sequence (see Figure 55).

0: No write collision occurred

1: A write collision has been detected.

5OVR

SPI Overrun error

This bit is set by hardware when the byte currently being received in the shift register

is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun

condition (OVR) on page 97). An interrupt is generated if SPIE = 1 in SPICR

0: No overrun error

1: Overrun error detected

4MODF

Mode Fault flag

This bit is set by hardware when the SS pin is pulled low in master mode (see

Master mode fault (MODF) on page 97). An SPI interrupt can be generated if

SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An

access to the SPICR register while MODF = 1 followed by a write to the SPICR

0: No master mode fault detected

1: A fault in master mode has been detected.

Reserved, must be kept cleared.

Table 55.

SPI master mode SCK frequency (continued)

Serial clock

SPR2

SPR1

SPR0

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