ST72324BJ2 datasheet(38/188 Pages) STMICROELECTRONICS

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Interrupts

ST72324B

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When an interrupt request is not serviced immediately, it is latched and then processed

when its software priority combined with the hardware priority becomes the highest one.

Note:

The hardware priority is exclusive while the software one is not. This allows the previous

process to succeed with only one interrupt.

Reset and TRAP can be considered as having the highest software priority in the decision

process.

7.2.2

Different interrupt vector sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable

type (reset, TRAP) and the maskable type (external or from internal peripherals).

7.2.3

Non-maskable sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register

(see Figure 18). After stacking the PC, X, A and CC registers (except for reset), the

corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to

disable interrupts (level 3). These sources allow the processor to exit Halt mode.

TRAP (non-maskable software interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced

according to the flowchart in Figure 18.

Reset

The reset source has the highest priority in the ST7. This means that the first current routine

has the highest software priority (level 3) and the highest hardware priority.

See the reset chapter for more details.

7.2.4

Maskable sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled

and if its own interrupt software priority (in ISPRx registers) is higher than the one currently

being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt

is latched and thus remains pending.

External interrupts

External interrupts allow the processor to Exit from Halt low power mode. External interrupt

sensitivity is software selectable through the External Interrupt Control register (EICR).

External interrupt triggered on edge will be latched and the interrupt request automatically

cleared upon entering the interrupt service routine.

If several input pins of a group connected to the same interrupt line are selected

simultaneously, these will be logically ORed.

Peripheral interrupts

Usually the peripheral interrupts cause the MCU to Exit from Halt mode except those

mentioned in Table 24: Interrupt mapping. A peripheral interrupt occurs when a specific flag

is set in the peripheral status registers and if the corresponding enable bit is set in the

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