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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72324BJ2 датащи(PDF) 96 Page - STMicroelectronics |
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ST72324BJ2 датащи(HTML) 96 Page - STMicroelectronics |
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96 / 188 page  On-chip peripherals ST72324B 96/188 The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition (OVR) on page 97). 10.4.4 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (see Figure 54). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 54 shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK, MISO and MOSI pins are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Figure 54. Data clock timing diagram(1) 1. This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. SCK MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB MISO (from master) MOSI (from slave) SS (to slave) Capture strobe CPHA = 1 MISO (from master) MOSI SS (to slave) Capture strobe CPHA = 0 (from slave) (CPOL = 1) SCK (CPOL = 0) SCK (CPOL = 1) SCK (CPOL = 0) MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB |
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