ST72324BJ2 datasheet(86/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST72324B

86/188

Control/Status Register (CSR)

5OPM

One Pulse Mode

0: One Pulse mode is not active.

1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the

OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the

generated pulse depends on the contents of the OC1R register.

4PWM

Pulse Width Modulation

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the

length of the pulse depends on the value of OC1R register; the period depends on

the value of OC2R register.

3:2

CC[1:0]

Clock Control

The timer clock mode depends on these bits.

00: Timer clock = fCPU/4

01: Timer clock = fCPU/2

10: Timer clock = fCPU/8

11: Timer clock = external clock (where available)

Note: If the external clock pin is not available, programming the external clock

configuration stops the counter.

1IEDG2

Input Edge 2

This bit determines which type of level transition on the ICAP2 pin will trigger the

capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

EXEDG

External Clock Edge

This bit determines which type of level transition on the external clock pin EXTCLK

will trigger the counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

CSR

Reset value: xxxx x0xx (xxh)

654

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

Reserved

R/W

Table 50.

CSR register description

Bit

Name

Function

7ICF1

Input Capture Flag 1

0: No Input Capture (reset value).

1: An Input Capture has occurred on the ICAP1 pin or the counter has reached the

OC2R value in PWM mode. To clear this bit, first read the SR register, then read or

write the low byte of the IC1R (IC1LR) register.

Table 49.

CR2 register description (continued)

Bit

Name

Function

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