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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72324BJ2 датащи(PDF) 84 Page - STMicroelectronics |
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ST72324BJ2 датащи(HTML) 84 Page - STMicroelectronics |
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84 / 188 page  On-chip peripherals ST72324B 84/188 10.3.6 Summary of timer modes 10.3.7 16-bit timer registers Each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. Control Register 1 (CR1) M Table 47. Summary of timer modes Mode Timer resources Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) One Pulse mode No Not recommended(1) 1. See note 4 in One Pulse mode on page 79. No Partially(2) 2. See note 5 in One Pulse mode on page 79. PWM mode Not recommended(3) 3. See note 4 in Pulse Width Modulation mode on page 81. No CR1 Reset value: 0000 0000 (00h) 7 654 32 10 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 R/W R/W R/W R/W R/W R/W R/W R/W Table 48. CR1 register description Bit Name Function 7ICIE Input Capture Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. 6OCIE Output Compare Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. 5TOIE Timer Overflow Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. |
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