ST72324BJ2 datasheet(95/188 Pages) STMICROELECTRONICS

95 / 188 page

ST72324B

On-chip peripherals

95/188

Master mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift

When data transfer is complete:

–

The SPIF bit is set by hardware

–

An interrupt request is generated if the SPIE bit is set and the interrupt mask in the

CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

An access to the SPICSR register while the SPIF bit is set.

A read to the SPIDR register.

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

Slave mode operation

In slave mode, the serial clock is received on the SCK pin from the master device.

To operate the SPI in slave mode:

Write to the SPICSR register to perform the following actions:

–

Select the clock polarity and clock phase by configuring the CPOL and CPHA bits

(see Figure 54). The slave must have the same CPOL and CPHA settings as the

master.

–

Manage the SS pin as described in Slave Select management on page 93 and

Figure 52. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must

be held low during byte transmission and pulled up between each byte to let the

slave write in the shift register.

Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI

I/O functions.

Slave mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift

The transmit sequence begins when the slave device receives the clock signal and the most

significant bit of the data on its MOSI pin.

When data transfer is complete:

–

The SPIF bit is set by hardware

–

An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR

Clearing the SPIF bit is performed by the following software sequence:

An access to the SPICSR register while the SPIF bit is set.

A write or a read to the SPIDR register.

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

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