ST72324BJ2 datasheet(32/188 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST72324B

32/188

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the

MCU can only be in two modes:

–

under full software control

–

in static safe reset

In these conditions, secure operation is always ensured for the application without the need

for external reset hardware.

During an LVD reset, the RESET pin is held low, thus permitting the MCU to reset other

devices.

Note:

The LVD allows the device to be used without any external reset circuitry.

If the medium or low thresholds are selected, the detection may occur outside the specified

operating voltage range. Below 3.8V, device operation is not guaranteed.

The LVD is an optional function which can be selected by option byte.

It is recommended to make sure that the VDD supply voltage rises monotonously when the

device is exiting from reset, to ensure the application functions properly.

Figure 16.

Low voltage detector vs reset

6.5.2

AVD (auxiliary voltage detector)

The AVD is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference

value and the VDD main supply. The VIT- reference value for falling voltage is lower than the

VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a

real-time status bit (AVDF) in the SICSR register. This bit is read only.

Caution:

The AVD function is active only if the LVD is enabled through the option byte (see

Section 14.1 on page 172).

Monitoring the VDD main supply

The AVD voltage threshold value is relative to the selected LVD threshold configured by

option byte (see Section 14.1 on page 172).

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the

VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing

software to shut down safely before the LVD resets the microcontroller. See Figure 17.

VDD

VIT+

RESET

VIT-

Vhys

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