ST72324BJ2 datasheet(44/188 Pages) STMICROELECTRONICS

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Interrupts

ST72324B

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7.6.2

External interrupt control register (EICR)

EICR

Reset value: 0000 0000 (00h)

654

IS11

IS10

IPB

IS21

IS20

IPA

Reserved

R/W

Table 18.

EICR register description

Bit

Name

Function

7:6

IS1[1:0]

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following

external interrupts:

- ei2 for port B [3:0] (see Table 19)

- ei3 for port B4 (see Table 20)

Bits 7 and 6 can only be written when I1 and I0 of the CC register are both set to 1

(level 3).

5IPB

Interrupt Polarity (for port B)

This bit is used to invert the sensitivity of port B [3:0] external interrupts. It can be

set and cleared by software only when I1 and I0 of the CC register are both set to 1

(level 3).

0: No sensitivity inversion

1: Sensitivity inversion

4:3

IS2[1:0]

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following

external interrupts:

- ei0 for port A[3:0] (see Table 21)

- ei1 for port F[2:0] (see Table 22)

Bits 4 and 3 can only be written when I1 and I0 of the CC register are both set to 1

(level 3).

2IPA

Interrupt Polarity (for port A)

This bit is used to invert the sensitivity of port A [3:0] external interrupts. It can be

set and cleared by software only when I1 and I0 of the CC register are both set to 1

(level 3).

0: No sensitivity inversion.

1: Sensitivity inversion.

1:0

Reserved, must always be kept cleared

Table 19.

Interrupt sensitivity - ei2

IS11

IS10

External interrupt sensitivity

IPB bit = 0

IPB bit = 1

Falling edge and low level

Rising edge and high level

Rising edge only

Falling edge only

Rising edge only

Rising and falling edge

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