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ST72324BJ2 датащи(PDF) 102 Page - STMicroelectronics

номер детали ST72324BJ2
подробное описание детали  8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
PDF  188 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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ST72324BJ2 датащи(HTML) 102 Page - STMicroelectronics

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On-chip peripherals
ST72324B
102/188
SPI Data I/O Register (SPIDR)
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note:
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Warning:
A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 50).
2SOD
SPI Output Disable
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1).
1: SPI output disabled.
1
SSM
SS Management
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Slave Select management
on page 93.
0: Hardware management (SS managed by external pin).
1: Software management (internal SS signal controlled by SSI bit. External SS pin
free for general-purpose I/O).
0SSI
SS Internal mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the
level of the SS slave select signal when the SSM bit is set.
0: Slave selected.
1: Slave deselected.
SPIDR
Reset value: undefined
7
654
32
10
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 56.
SPICSR register description (continued)
Bit
Name
Function



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